• Skip to primary navigation
  • Skip to main content
  • Skip to footer

Vonoff

SkyKo Comics and videos about Semiconductor and nanotechnology | 반도체 만화

  • HOME
  • COMICS & VIDEOS
  • ABOUT
  • CONTACT
Home / Comics / A trip down memory lane -#1: Memory to reduce latency gap

A trip down memory lane -#1: Memory to reduce latency gap

November 25, 2017 By sky Leave a Comment

Summary

Processors and memory have always differed in priorities, creating an ever-increasing latency gap. New memory types have been introduced to bridge this gap, but will they be enough?
  • select language:
  • EN
  • KR
DRAM as a main memory
P1
Growing gap between processor and memory speed
P2
different priority between processor and memory
P3
SRAM cache memory to bridge the latency gap between cpu and memory
P4
memory trade-offs
P5
SSD to bridge the latency gap between DRAM and HDD storage
P6
NVMe SSD using PCIe interface
P7
Emerging high performance NVMe SSDs using PCI interface - Micron's NVMe SSDs
ssd data retention in extrem conditions
P8
Please consider becoming a sponsor of my work
  • Scroll to:
  • Ep1
  • Next

Share this post : on Twitter on Facebook on LinkedIn

Reference

  1. Carlos , Carvalho. Universidade do Minho. “The Gap between Processor and Memory Speeds.”
  2. Zahran, M. New York University. Lecture 3: "The Memory System."
  3. Onur , Mutlu, et al. Carnegie Mellon University. “The Main Memory System: Challenges and Opportunities.”
  4. Lee, Donghyuk, et al. Carnegie Mellon University. “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture.”
  5. “Samsung NVMe SSD.”
  6. Pratt, Tom. Micron. “The Real World of Emerging Memories.”

Share this post : on Twitter on Facebook on LinkedIn

Related posts:

A trip down memory lane -#2: The sorrow of DRAM scaling challenge A trip down memory lane -#3 : DRAM vs. emerging memories Default Thumbnail기억을 쫓아서-#1 – CPU와 메모리간 병목현상 극복 A_Trip_Down_Memory_Lane-featured-2기억을 쫓아서-#2 – 새로운 차세대메모리 등장 Default Thumbnail기억을 쫓아서-#3 – DRAM 새로운 3D power scaling 시대로 plasma-doping-dose-accuracy-thumnail2Dose accuracy in plasma doping

Filed Under: Comics, Memory technology, Nanotechnology Tagged With: Cache memory, data retention, DRAM, Latency gap, Memory heirarchy, Memory wall, NAND flash, NVMe SSD, SRAM, SSD, 병목현상, 캐시메모리

Reader Interactions

Leave a Reply Cancel reply

Your email address will not be published. Required fields are marked *

Footer

  • skyonsky@gmail.com
  • About
  • Comics

All work © Sky Ko -